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A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Zhao, Xiaoteng, Chen, Yong, Wang, Lin, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS[C], 2021, 131-134.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco; et al.
Favorite | TC[WOS]:6 TC[Scopus]:9 | Submit date：2021/09/20
4-level Pulse Amplitude Modulation (Pam-4)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Frequency Detector (Fd)  Half-rate  Negative (Nnc) Net Current  Positive (Pnc)  Reference Less  Single Loop  Zero (Znc)  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[Scopus]:16 | Submit date：2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao, X., Chen, Y., Mak, P. I., Martins, R. P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao, X.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Single loop  full-rate  bang-bang  bang-bang clock and recovery circuit