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An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme Journal article
Hao, Junyan, Zhang, Minglei, Liu, Zijian, Zhang, Yanbo, Liu, Shubin, Zhu, Zhangming, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Hao, Junyan;  Zhang, Minglei;  Liu, Zijian;  Zhang, Yanbo;  Liu, Shubin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/12/26
Analog-to-digital Converter (Adc)  Parallel Quantization And Amplification  Pipelined Adc  Time-domain (Td) Adc  Voltage-to-time Converter (Vtc)  
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Journal article
Zhang,Chenghao, Wei,Jiangbo, Chen,Yong, Liu,Maliang, Yang,Yintang. A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3179-3193.
Authors:  Zhang,Chenghao;  Wei,Jiangbo;  Chen,Yong;  Liu,Maliang;  Yang,Yintang
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Cmos  Folding  Gated Ring Oscillator (Gro)  Interpolation  Pulse Generator (Pg)  Time Domain (Td)  Voltage Domain (Vd)  
Low-Power Nyquist ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:131-180
Authors:  Minglei Zhang;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[Scopus]:1 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Low Supply Voltage  Pipeline  Successive Approximation Register (Sar)  Time-domain Converter (Tdc)  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:16  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui P. Martins. A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration[C]:IEEE, 2021.
Authors:  Minglei Zhang;  Yan Zhu;  Chi-Hang Chan;  Rui P. Martins
Favorite | TC[Scopus]:13 | Submit date：2021/09/20
Background  Input Independent  Time Domain Adc  Time-interleaved Adc  Timing Skew Calibration  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
Zhang,Minglei, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps[J]. IEEE Journal of Solid-State Circuits, 2020, 55(12), 3225-3235.
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:36 TC[Scopus]:43  IF:4.6/5.6 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  High-speed Adc  Metastability  Process  Supply Voltage  And Temperature (Pvt) Robustness  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:29 TC[Scopus]:43  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)  
A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS Journal article
Liu, J., Chan, C.H., Sin, S. W., U, S.P., Martins, R. P.. A 4x Time-Domain Interpolation 6-bit 3.4GS/s 12.6mW Flash ADC in 65nm CMOS[J]. Journal of Semiconductor Technology and Science, 2016, 395-404.
Authors:  Liu, J.;  Chan, C.H.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |   IF:0.5/0.3 | Submit date：2022/01/24
Flash ADC  time comparator  4x time-domain interpolation  SR-latch