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A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLYCurrent Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density Conference paper
Ma, Qiaobo, Li, Huihua, Shi, Jiahao, Jiang, Yang, Martins, Rui, Mak, Pui In. A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLYCurrent Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 22-4.
Authors:  Ma, Qiaobo;  Li, Huihua;  Shi, Jiahao;  Jiang, Yang;  Martins, Rui; et al.
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Power System Measurements  Buck Converters  Density Measurement  Volume Measurement  Switches  High-voltage Techniques  Control Systems  
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS Conference paper
Qin, Xinyu, Jin, Yichen, Wang, Guoxing, Sin, Sai Weng, Ortmanns, Maurits, Lian, Yong, Qi, Liang. A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Qin, Xinyu;  Jin, Yichen;  Wang, Guoxing;  Sin, Sai Weng;  Ortmanns, Maurits; et al.
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Multi-stage Noise Shaping  Application Specific Integrated Circuits  Quantization (Signal)  Cmos Integrated Circuits  
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation Conference paper
Shen, Xinyu, Zhang, Zhao, Chen, Yong, Li, Yixi, Zhang, Yidan, Li, Guike, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Chen, Yong;  Li, Yixi;  Zhang, Yidan; et al.
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Temperature Sensors  Phase Noise  Linearity  Voltage  Detectors  Jitter  Delay Lines  
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC Conference paper
He, Pengyu, Zhao, Yuanzhe, Xie, Heng, Wang, Yang, Yin, Shouyi, Li, Li, Zhu, Yan, Martins, R. P., Chan, Chi Hang, Zhang, Minglei. A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  He, Pengyu;  Zhao, Yuanzhe;  Xie, Heng;  Wang, Yang;  Yin, Shouyi; et al.
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Power Demand  In-memory Computing  Throughput  Energy Efficiency  Hardware  Common Information Model (Computing)  Artificial Intelligence  
A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from-25 to 85°C Conference paper
Zhao, Guangshu, Xie, Chao, Wang, Chenxi, Jiang, Yang, Zhang, Milin, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from-25 to 85°C[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Zhao, Guangshu;  Xie, Chao;  Wang, Chenxi;  Jiang, Yang;  Zhang, Milin; et al.
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A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D Integration Conference paper
Huang, Junwei, Tong, Zhiguo, Mao, Xiangyu, Lam, Chi Seng, Martins, Rui P., Lu, Yan. A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D Integration[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Huang, Junwei;  Tong, Zhiguo;  Mao, Xiangyu;  Lam, Chi Seng;  Martins, Rui P.; et al.
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Performance Evaluation  Transient Response  Buck Converters  Program Processors  Power Supplies  Voltage  High-voltage Techniques  
A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUTAugmentation Conference paper
Li, Huihua, Ma, Qiaobo, Jiang, Yang, Martins, Rui, Mak, Pui In. A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUTAugmentation[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 22-2.
Authors:  Li, Huihua;  Ma, Qiaobo;  Jiang, Yang;  Martins, Rui;  Mak, Pui In
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A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs Conference paper
Mao, Xiangyu, Huang, Junwei, Tong, Zhiguo, Martins, Rui, Lu, Yan. A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 9-4.
Authors:  Mao, Xiangyu;  Huang, Junwei;  Tong, Zhiguo;  Martins, Rui;  Lu, Yan
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Transient Response  Buck Converters  Regulators  Multicore Processing  Capacitors  Power System Dynamics  Inductors  
A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control Conference paper
PENG YATAO, Jad Benserhir, Yating Zou, Edoardo Charbon. A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 32-4.
Authors:  PENG YATAO;  Jad Benserhir;  Yating Zou;  Edoardo Charbon
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Temperature  Superconducting Integrated Circuits  Qubit  Linearity  Cryogenics  Superconducting Filters  Superconducting Device Noise  
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS Conference paper
Yang, Jian, Xu, Tailong, Meng, Xi, Li, Zhenghao, Yin, Jun, Mak, Pui In, Martins, Rui P., Pan, Quan. A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 17-2.
Authors:  Yang, Jian;  Xu, Tailong;  Meng, Xi;  Li, Zhenghao;  Yin, Jun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2024/06/05
Wireless Communication  Time-frequency Analysis  Frequency Synthesizers  Switches  Transforms  Filtering Algorithms  Frequency Estimation