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A Series-LC-Assisted Oscillator Achieving -140.2dBc/Hz Phase Noise and 187.5dBc/Hz FoM at 10MHz Offset From 10.7GHz Journal article
Zhan, Xiangxun, Yin, Jun, Martins, Rui P., Mak, Pui In. A Series-LC-Assisted Oscillator Achieving -140.2dBc/Hz Phase Noise and 187.5dBc/Hz FoM at 10MHz Offset From 10.7GHz[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025, 72(2), 389 - 393.
Authors:  Zhan, Xiangxun;  Yin, Jun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/13
Phase Noise (Pn)  Figure Of Merit (Fom)  Series Lc  Oscillator  Frequency Tuning Range (Ftr)  
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction Journal article
Xu, Tailong, Li, Haoran, Meng, Xi, Zhan, Xiangxun, Peng, Yatao, Yin, Jun, Yang, Shiheng, Fan, Chao, Huang, Zhixiang, Martins, Rui P., Mak, Pui In. Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.
Authors:  Xu, Tailong;  Li, Haoran;  Meng, Xi;  Zhan, Xiangxun;  Peng, Yatao; et al.
Favorite | TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/22
Gain-boosting Phase Detector  Jitter  Phase Noise  Phase-locked Loop  Reference Spur  Reference-sampling  
A 50-Gb/s 1.35-pJ/b PAM-4 VCSEL Transmitter With Three-Tap Asymmetric FFE and Current-Resue Technique in 40-nm CMOS Journal article
Yang, Jian, Peng, Yi, Yin, Jun, Mak, Pui In, Pan, Quan. A 50-Gb/s 1.35-pJ/b PAM-4 VCSEL Transmitter With Three-Tap Asymmetric FFE and Current-Resue Technique in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Yang, Jian;  Peng, Yi;  Yin, Jun;  Mak, Pui In;  Pan, Quan
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2025/01/13
Asymmetric Equalization  Bandwidth Extension  Binary-to-thermal (B2t)  Cmos  Current Reuse  Driver  Feedforward Equalization (Ffe)  Four-level Pulse Amplitude Modulation (Pam-4)  Light-current–voltage (L-i–v)  Optical Transmitter (Tx)  Vertical-cavity Surface-emitting Laser (Vcsel)  
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3866-3876.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/05/16
Compute-in-memory (Cim)  Deep Neural Network (Dnn)  Embedded Dynamic Random Access Memory (Edram)  Input-sparsity  Single-finger (Sf)  Weight Update/refresh  
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization Journal article
Li, Jixuan, Li, Ke, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Li, Jixuan;  Li, Ke;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Convolutional Neural Network (Cnn)  Digital Signal Processing (Dsp)  Field-programmable Gate Array (Fpga)  Processing Unit (Pe) Utilization  Residual Block  
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 4996-5004.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization Conference paper
Xin, Guoqiang, Tan, Fei, Li, Junde, Chen, Junren, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 882-887.
Authors:  Xin, Guoqiang;  Tan, Fei;  Li, Junde;  Chen, Junren;  Yu, Wei Han; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
5t-sram  Analog Non-uniform Quantization (Anuq)  Computing-in-memory (Clm)  Machine Learning (Ml)  Matrix-vector Multiplication (Mvm)  Partial Sum Boosting (Psb)  
A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna–TRX Interface Journal article
Yang, Zhizhan, Yin, Jun, Yu, Wei Han, Zhang, Haochen, Martins, Rui P., Mak, Pui In. A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna–TRX Interface[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(11), 3670-3682.
Authors:  Yang, Zhizhan;  Yin, Jun;  Yu, Wei Han;  Zhang, Haochen;  Martins, Rui P.; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/06/05
Antenna  Energy Efficiency  Event-driven  Internet Of Things (Iot)  Power Amplifier (Pa)  Rf Transceiver  Radio-frequency Identification (Rfid)  Ultra-low Power (Ulp)  Voltage-controlled Oscillator (Vco)