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Correction to: E3 ubiquitin ligase UBR5 modulates circadian rhythm by facilitating the ubiquitination and degradation of the key clock transcription factor BMAL1 (Acta Pharmacologica Sinica, (2024), 10.1038/s41401-024-01290-z) Other
2024-12-01
Authors:  Duan, Chun Yan;  Li, Yue;  Zhi, Hao Yu;  Tian, Yao;  Huang, Zheng Yun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/07/04
A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3866-3876.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/05/16
Compute-in-memory (Cim)  Deep Neural Network (Dnn)  Embedded Dynamic Random Access Memory (Edram)  Input-sparsity  Single-finger (Sf)  Weight Update/refresh  
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization Conference paper
Xin, Guoqiang, Tan, Fei, Li, Junde, Chen, Junren, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 882-887.
Authors:  Xin, Guoqiang;  Tan, Fei;  Li, Junde;  Chen, Junren;  Yu, Wei Han; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
5t-sram  Analog Non-uniform Quantization (Anuq)  Computing-in-memory (Clm)  Machine Learning (Ml)  Matrix-vector Multiplication (Mvm)  Partial Sum Boosting (Psb)  
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 4996-5004.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization Journal article
Li, Jixuan, Li, Ke, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Li, Jixuan;  Li, Ke;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Convolutional Neural Network (Cnn)  Digital Signal Processing (Dsp)  Field-programmable Gate Array (Fpga)  Processing Unit (Pe) Utilization  Residual Block  
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
Effects of Physical Exercise Breaks on Executive Function in a Simulated Classroom Setting: Uncovering a Window into the Brain Journal article
Yu, Qian, Zhang, Zhihao, Ludyga, Sebastian, Erickson, Kirk I., Cheval, Boris, Hou, Meijun, Pindus, Dominika M., Hillman, Charles H., Kramer, Arthur F., Falck, Ryan S., Liu-Ambrose, Teresa, Kuang, Jin, Mullen, Sean P., Kamijo, Keita, Ishihara, Toru, Raichlen, David A., Heath, Matthew, Moreau, David, Werneck, André O., Herold, Fabian, Zou, Liye. Effects of Physical Exercise Breaks on Executive Function in a Simulated Classroom Setting: Uncovering a Window into the Brain[J]. Advanced Science, 2024, 12(3), 2406631.
Authors:  Yu, Qian;  Zhang, Zhihao;  Ludyga, Sebastian;  Erickson, Kirk I.;  Cheval, Boris; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:14.3/16.3 | Submit date：2024/12/26
Brain Health  Cerebrovascular Health  Effective Connectivity  Microvascular Health  Sedentary Behavior  Young Adults  
A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna–TRX Interface Journal article
Yang, Zhizhan, Yin, Jun, Yu, Wei Han, Zhang, Haochen, Martins, Rui P., Mak, Pui In. A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna–TRX Interface[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59(11), 3670-3682.
Authors:  Yang, Zhizhan;  Yin, Jun;  Yu, Wei Han;  Zhang, Haochen;  Martins, Rui P.; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/06/05
Antenna  Energy Efficiency  Event-driven  Internet Of Things (Iot)  Power Amplifier (Pa)  Rf Transceiver  Radio-frequency Identification (Rfid)  Ultra-low Power (Ulp)  Voltage-controlled Oscillator (Vco)  
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/05
Neural Network (Nn)  Transformer  Embedded Dynamic Random-access Memory (Edram)  Compute-in-memory (Cim)  Systolic  Flexible Dataflow  
Deadly yet Preventable? Lessons from South Korea's Halloween Crowd Crush Journal article
Su, Zhaohui, Cheshmehzangi, Ali, Bentley, Barry L., McDonnell, Dean, Ahmad, Junaid, Šegalo, Sabina, Da Veiga, Claudimar P., Xiang, Yu Tao. Deadly yet Preventable? Lessons from South Korea's Halloween Crowd Crush[J]. Disaster Medicine and Public Health Preparedness, 2024, 18.
Authors:  Su, Zhaohui;  Cheshmehzangi, Ali;  Bentley, Barry L.;  McDonnell, Dean;  Ahmad, Junaid; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.9/1.9 | Submit date：2024/12/05
COVID-19  disaster preparedness  health policy  public health  public safety