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A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation Conference paper
Shen, Xinyu, Zhang, Zhao, Chen, Yong, Li, Yixi, Zhang, Yidan, Li, Guike, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Chen, Yong;  Li, Yixi;  Zhang, Yidan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Temperature Sensors  Phase Noise  Linearity  Voltage  Detectors  Jitter  Delay Lines  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM Conference paper
Shen, Xinyu, Zhang, Zhao, Li, Guike, Chen, Yong, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM[C]:IEEE, 2023, 257-260.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Li, Guike;  Chen, Yong;  Qi, Nan; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2024/02/22
Cmos.  Fractional-n(Fn)  Loop Bandwidth Tracking  Ring Sampling Phase-locked Loop (Rspll)  Wideband  
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O Journal article
Chen, Sikai, You, Mingyang, Yang, Yunqi, Jin, Ye, Lin, Ziyi, Li, Yihong, Li, Leliang, Li, Guike, Xie, Yujun, Zhang, Zhao, Wang, Binhao, Tang, Ningfeng, Liu, Faju, Fang, Zheyu, Liu, Jian, Wu, Nanjian, Chen, Yong, Liu, Liyuan, Zhu, Ninghua, Li, Ming, Qi, Nan. A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(11), 4271-4282.
Authors:  Chen, Sikai;  You, Mingyang;  Yang, Yunqi;  Jin, Ye;  Lin, Ziyi; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2023/12/04
Baud-rate  Cdr  Chiplet  Cmos  Multi-chip Module (Mcm)  Optical I/o  Optical Receiver  Silicon Photonics  Tia  
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS Conference paper
Zhang, Zhao, Zhang, Zhaoyu, Chen, Yong, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Zhang, Zhao;  Zhang, Zhaoyu;  Chen, Yong;  Qi, Nan;  Liu, Jian; et al.
Favorite | TC[Scopus]:1 | Submit date：2024/02/23
4.7 A O.4V-VDD2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrmsJitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur Conference paper
Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu. 4.7 A O.4V-VDD2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrmsJitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2023, 86-88.
Authors:  Zhao Zhang;  Xinyu Shen;  Zhaoyu Zhang;  Guike Li;  Nan Qi; et al.
Favorite | TC[Scopus]:7 | Submit date：2023/08/03
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects Journal article
He, Jian, Lu, Donglai, Xue, Haiyun, Chen, Sikai, Liu, Han, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Liu, Liyuan, Wu, Nanjian, Yu, Ningmei, Liu, Fengman, Xiao, Xi, Chen, Yong, Qi, Nan. Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(11), 4345-4357.
Authors:  He, Jian;  Lu, Donglai;  Xue, Haiyun;  Chen, Sikai;  Liu, Han; et al.
Favorite | TC[WOS]:17 TC[Scopus]:21  IF:5.2/4.5 | Submit date：2022/08/05
400gbase-sr8  Continuous-time Linear Equalizer (Ctle)  Four-level Pulse Amplitude Modulation (Pam-4)  Integrated Circuit Modeling  Nonlinear Optics  Optical Receivers  Optical Superlattices  Optical Transmitters  Sige Bicmos  Trans-impedance Amplifier (Tia)  Transceiver (Trx)  Transceivers  Vertical Cavity Surface Emitting Lasers  Vertical-cavity-surface-emitting Laser (Vcsel) Driver  
WNT16 from decidual stromal cells regulates HTR8/SVneo trophoblastic cell function via AKT/beta-catenin pathway Journal article
Li, Xinyi, Shi, Jiaxin, Zhao, Weijie, Huang, Xixi, Cui, Liyuan, Liu, Lu, Jin, Xueling, Li, Djin, Zhang, Xuan, Du, Meirong. WNT16 from decidual stromal cells regulates HTR8/SVneo trophoblastic cell function via AKT/beta-catenin pathway[J]. Reproduction (Cambridge, England), 2022, 163(5), 241-250.
Authors:  Li, Xinyi;  Shi, Jiaxin;  Zhao, Weijie;  Huang, Xixi;  Cui, Liyuan; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2022/09/21
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
Liao, Qiwen, Zhang, Yuguang, Ma, Siyuan, Wang, Lei, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Wu, Nanjian, Liu, Liyuan, Chen, Yong, Xiao, Xi, Qi, Nan. A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 767-780.
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang; et al.
Favorite | TC[WOS]:26 TC[Scopus]:33  IF:4.6/5.6 | Submit date：2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)