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A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM Conference paper
Ren, Hongyu, Huang, Yunbo, Yang, Zunsong, Chen, Tianle, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Li, Zhongmao, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C], 2024, 113-116.
Authors:  Ren, Hongyu;  Huang, Yunbo;  Yang, Zunsong;  Chen, Tianle;  Meng, Xianghe; et al.
Favorite |  | Submit date：2024/12/05
Clock Generator  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase-Locked Loop (PLL)  Reference Sampling  Type-II  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:21 TC[Scopus]:22  IF:5.2/4.5 | Submit date：2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[Scopus]:16 | Submit date：2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter Journal article
Ge,Xinyi, Chen,Yong, Zhao,Xiaoteng, Mak,Pui In, Martins,Rui P.. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236.
Authors:  Ge,Xinyi;  Chen,Yong;  Zhao,Xiaoteng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:19  IF:2.8/2.8 | Submit date：2021/03/09
Bang-bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Binary  Fourier Series  Jitter Generation (Jgen)  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Linear Phase Detector  Loop Filter (Lf)  Sinking Area  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
Yang X., Zhu Y., Chan C.-H., Seng-Pan U., Martins R.P.. Analysis of common-mode interference and jitter of clock receiver circuits with improved topology[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(6), 1819-1829.
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:7 TC[Scopus]:9 | Submit date：2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators Conference paper
Jiang Y., Wong K.-F., Cai C.-Y., Sin S.-W., U S.-P., Martins R.P.. A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators[C], 2011, 1011-1014.
Authors:  Jiang Y.;  Wong K.-F.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/02/11
Clock-jitter Sensitivity  Continuous-time  Sigma-delta Modulator  Switched Current Dac