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A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur Journal article
Huang, Yunbo, Chen, Yong, Zhao, Bo, Mak, Pui In, Martins, Rui P.. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475.
Authors:  Huang, Yunbo;  Chen, Yong;  Zhao, Bo;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:11  IF:5.2/4.5 | Submit date：2023/05/02
Cmos  Type-i Sampling Phase-locked Loop (S-pll)  Voltage-controlled Oscillator (Vco)  Reference (Ref) Feedthrough Suppression  Figure-of-merit (Fom)  Phase-detection Gain (Kpd)  Sampling Phase Detector (S-pd)  
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops Journal article
Huang, Yunbo, Chen, Yong, Mak, Pui In, Martins, Rui P.. Universal Stability Criterion for Type-I Sampling Phase-Locked Loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(4), 1351-1355.
Authors:  Huang, Yunbo;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.0/3.7 | Submit date：2023/05/02
Given Phase Margin (Pm)  Linear Time-variant (Ltv) Mode  Sampling Phase-locked Loop (S-pll)  Sub-sampling Pll (ss-Pll)  Type-i  Voltage-controlled Oscillator (Vco)  
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:9  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
Huang, Yunbo, Chen, Yong, Jiao, Hailong, Mak, Pui In, Martins, Rui P.. A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(9), 3093-3097.
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:20 TC[Scopus]:19  IF:4.0/3.7 | Submit date：2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)