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A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs Journal article
Lu, Zhifei, Zhang, Boyuan, Peng, Yutao, Peng, Xizhu, Tang, He, Pu, Jie, Qin, Ling, Guo, Mingqiang. A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025, 72(1), 48-52.
Authors:  Lu, Zhifei;  Zhang, Boyuan;  Peng, Yutao;  Peng, Xizhu;  Tang, He; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/12/26
Background Calibration  Fast Convergence  Neural-network-based Extraction Module  Nn-based Calibration  Time-interleaved Adc (Ti Adc)  Timing Mismatch Calibration  
A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer[J]. IEEE Journal of Solid-State Circuits, 2024, 59(12), 4211-4224.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/12/05
Analog-to-digital Converter (Adc)  Global Dither Injection (Gdi)  Input Buffer (Ibf)  Self-adaptive Current Compensation (Sacc)  Sturdy Ring Amplifier (sRingamp)  Time-interleaved (Ti) Adc  Timing Skew Calibration  
A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator Journal article
Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi. A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 1-13.
Authors:  Yue Hu;  Yuekai Liu;  Xinyu Qin;  Yan Liu;  Mingqiang Guo; et al.
Adobe PDF | Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2023/08/22
Continuous-time Delta-sigma Modulator (Dsm)  Time-interleaved (Ti)  Cascaded Integrator Of Distributed Feedforward (Ciff)  Excess Loop Delay (Eld) Compensation  
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
Guo, Mingqiang, Sin, Sai Weng, Qi, Liang, Xu, Dengke, Wang, Guoxing, Martins, Rui P.. Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(6), 2564 - 2569.
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing; et al.
Adobe PDF | Favorite | TC[WOS]:5 TC[Scopus]:3  IF:4.0/3.7 | Submit date：2022/05/17
Adc  Time-interleaved  Timing Mismatch  Background  Calibration.  
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Guo Mingqiang, Sin Sai-Weng, Rui P. Martins. Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs[C]:IEEE, 2021, 248 - 249.
Authors:  Guo Mingqiang;  Sin Sai-Weng;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2022/05/13
Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:15 TC[Scopus]:17  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui P. Martins. A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration[C]:IEEE, 2021.
Authors:  Minglei Zhang;  Yan Zhu;  Chi-Hang Chan;  Rui P. Martins
Favorite | TC[Scopus]:13 | Submit date：2021/09/20
Background  Input Independent  Time Domain Adc  Time-interleaved Adc  Timing Skew Calibration  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
Jiang,Wenning, Zhu,Yan, Chan,Chi Hang, Murmann,Boris, Martins,Rui Paulo. A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 68(2), 557-568.
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite | TC[WOS]:30 TC[Scopus]:37  IF:5.2/4.5 | Submit date：2021/03/04
Analog-to-digital Converter  Sar Adc  Time-interleaved Adc  Current Integrating Sampler  Background Timing Skew Calibration  Timing Skew  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,Rui P.. A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications[J]. IEEE Access, 2020, 8, 138944-138954.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite | TC[WOS]:19 TC[Scopus]:24  IF:3.4/3.7 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
Guo Mingqiang, Mao Jiaji, Sin Sai-Weng, Wei Hegong, Rui P. Martins. A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 55(3), 693-705.
Authors:  Guo Mingqiang;  Mao Jiaji;  Sin Sai-Weng;  Wei Hegong;  Rui P. Martins
Adobe PDF | Favorite | TC[WOS]:53 TC[Scopus]:59  IF:4.6/5.6 | Submit date：2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch