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A 180MHz 45.3% Peak Efficiency Isolated Converter Using Q-Downsize Class-D Power Amplifier with Inherent Shoot-Through Current Blocking and High Tolerance for Efficiency Despite Frequency Misalignments Conference paper
XIA TIAN, CHEN QIUJIN, WANG SHUJING, RUI MARTINS, HUANG MO. A 180MHz 45.3% Peak Efficiency Isolated Converter Using Q-Downsize Class-D Power Amplifier with Inherent Shoot-Through Current Blocking and High Tolerance for Efficiency Despite Frequency Misalignments[C], 2025.
Authors:  XIA TIAN;  CHEN QIUJIN;  WANG SHUJING;  RUI MARTINS;  HUANG MO
Favorite |  | Submit date：2024/11/28
A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate during Load Transients Conference paper
YANG JIACHENG, R. P. MARTINS, HUANG MO. A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate during Load Transients[C], 2025.
Authors:  YANG JIACHENG;  R. P. MARTINS;  HUANG MO
Favorite |  | Submit date：2024/11/28
A Series-LC-Assisted Oscillator Achieving -140.2dBc/Hz Phase Noise and 187.5dBc/Hz FoM at 10MHz Offset From 10.7GHz Journal article
Zhan, Xiangxun, Yin, Jun, Martins, Rui P., Mak, Pui In. A Series-LC-Assisted Oscillator Achieving -140.2dBc/Hz Phase Noise and 187.5dBc/Hz FoM at 10MHz Offset From 10.7GHz[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025, 72(2), 389 - 393.
Authors:  Zhan, Xiangxun;  Yin, Jun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/13
Phase Noise (Pn)  Figure Of Merit (Fom)  Series Lc  Oscillator  Frequency Tuning Range (Ftr)  
A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation Journal article
Zhang, Ran, Cen, Xueru, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Martins, Rui P., Sin, Sai Weng. A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, 1-13.
Authors:  Zhang, Ran;  Cen, Xueru;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2025/01/22
Dac Driver  Dynamic Amplifier  Machine Learning (Ml)  Mixed-signal Multiply-and-accumulate (Mac)  Multi-bit Neural Network  
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction Journal article
Xu, Tailong, Li, Haoran, Meng, Xi, Zhan, Xiangxun, Peng, Yatao, Yin, Jun, Yang, Shiheng, Fan, Chao, Huang, Zhixiang, Martins, Rui P., Mak, Pui In. Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.
Authors:  Xu, Tailong;  Li, Haoran;  Meng, Xi;  Zhan, Xiangxun;  Peng, Yatao; et al.
Favorite | TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/22
Gain-boosting Phase Detector  Jitter  Phase Noise  Phase-locked Loop  Reference Spur  Reference-sampling  
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme Journal article
Hao, Junyan, Zhang, Minglei, Liu, Zijian, Zhang, Yanbo, Liu, Shubin, Zhu, Zhangming, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Hao, Junyan;  Zhang, Minglei;  Liu, Zijian;  Zhang, Yanbo;  Liu, Shubin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/12/26
Analog-to-digital Converter (Adc)  Parallel Quantization And Amplification  Pipelined Adc  Time-domain (Td) Adc  Voltage-to-time Converter (Vtc)  
A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer[J]. IEEE Journal of Solid-State Circuits, 2024, 59(12), 4211-4224.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/12/05
Analog-to-digital Converter (Adc)  Global Dither Injection (Gdi)  Input Buffer (Ibf)  Self-adaptive Current Compensation (Sacc)  Sturdy Ring Amplifier (sRingamp)  Time-interleaved (Ti) Adc  Timing Skew Calibration  
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving - 28.5-dBm Sensitivity Journal article
Chen, Qiujin, Xia, Tian, Hu, Tingxu, Wang, Yuanfei, Lu, Yan, Martins, Rui P., Huang, Mo. A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving - 28.5-dBm Sensitivity[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Chen, Qiujin;  Xia, Tian;  Hu, Tingxu;  Wang, Yuanfei;  Lu, Yan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2025/01/13
Energy Harvesting  Maximum Power Point Tracking (Mppt)  Rf  Single-ended Rectifier  Temperature Consistency  
0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation Journal article
Lee, Chon Fai, Chi-Wa, U., Martins, Rui P., Lam, Chi Seng. 0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 5040-5053.
Authors:  Lee, Chon Fai;  Chi-Wa, U.;  Martins, Rui P.;  Lam, Chi Seng
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/05
Bandgap Voltage Reference  Reverse Bandgap  Nonlinear Current  Leakage Current  Temperature Coefficient  Internet Of Things  Energy Harvesting  
A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3866-3876.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/05/16
Compute-in-memory (Cim)  Deep Neural Network (Dnn)  Embedded Dynamic Random Access Memory (Edram)  Input-sparsity  Single-finger (Sf)  Weight Update/refresh