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A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs Journal article
Lu, Zhifei, Zhang, Boyuan, Peng, Yutao, Peng, Xizhu, Tang, He, Pu, Jie, Qin, Ling, Guo, Mingqiang. A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025, 72(1), 48-52.
Authors:  Lu, Zhifei;  Zhang, Boyuan;  Peng, Yutao;  Peng, Xizhu;  Tang, He; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/12/26
Background Calibration  Fast Convergence  Neural-network-based Extraction Module  Nn-based Calibration  Time-interleaved Adc (Ti Adc)  Timing Mismatch Calibration  
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme Journal article
Hao, Junyan, Zhang, Minglei, Liu, Zijian, Zhang, Yanbo, Liu, Shubin, Zhu, Zhangming, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC with Dual-Path Time-Assisted Residue Generation Scheme[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Hao, Junyan;  Zhang, Minglei;  Liu, Zijian;  Zhang, Yanbo;  Liu, Shubin; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/12/26
Analog-to-digital Converter (Adc)  Parallel Quantization And Amplification  Pipelined Adc  Time-domain (Td) Adc  Voltage-to-time Converter (Vtc)  
A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A 12-GS/s 12-b 4 × Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer[J]. IEEE Journal of Solid-State Circuits, 2024, 59(12), 4211-4224.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/12/05
Analog-to-digital Converter (Adc)  Global Dither Injection (Gdi)  Input Buffer (Ibf)  Self-adaptive Current Compensation (Sacc)  Sturdy Ring Amplifier (sRingamp)  Time-interleaved (Ti) Adc  Timing Skew Calibration  
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:4 TC[Scopus]:3  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering Journal article
Li, Ke, Gong, Haoyu, Xianyu, Congzhou, Li, Zhensheng, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Ke;  Gong, Haoyu;  Xianyu, Congzhou;  Li, Zhensheng;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2025/01/13
Analog-to-digital Converter (Adc)  Cascade Of Integrators With Feedforward (Ciff)  Continuous Time (Ct)  Ct Pipeline (Ctp)  Excess Loop Delay (Eld)  Low-pass Filter (Lpf)  Multistage Noise-shaping (Mash)  Offset Calibration  Signal Transfer Function (Stf) Peaking  
A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor Journal article
Cheng, Kai, Chen, Yong, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Cheng, Kai;  Chen, Yong;  Stefano, Crovetti Paolo;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:1.8/1.7 | Submit date：2024/06/05
Analog-to-digital Converter (Adc)  Capacitive Digital-to-analog Converters (Cdacs)  Cryptography  Entropy  National Institute Of StAndards And Technology (Nist)  Successive Approximation Register (Sar)  Thermal Noise  True Random Number Generator (Trng)  
A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:5 TC[Scopus]:6  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:  Tan, Gaofeng;  Qin, Xinyu;  Liu, Yan;  Guo, Mingqiang;  Sin, Sai Weng; et al.
Favorite | TC[WOS]:3 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2024/02/23
0-x Mash  Analog-to-digital Converter (Adc)  Anti-aliasing Filtering  Continuous Time (Ct)  Maximum Stable Amplitude (Msa)  Multi-stage Noise Shaping (Mash)  
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching