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A 256 x 192-Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging Journal article
Zou, Chaorui, Ou, Yaozhong, Zhu, Yan, Rui P. Martins, Chi-Hang Chan, Minglei, Zhang. A 256 x 192-Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3525-3537.
Authors:  Zou, Chaorui;  Ou, Yaozhong;  Zhu, Yan;  Rui P. Martins;  Chi-Hang Chan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/08/30
3-d Imaging  Analog Frontend (Afe)  Background Light Compensation  Current-integrating (Ci)  Direct Timeof-flight (Dtof)  Lidar  Pixel Accumulation  Transimpedance Amplifier (Tia)  
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization Conference paper
Xin, Guoqiang, Tan, Fei, Li, Junde, Chen, Junren, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 882-887.
Authors:  Xin, Guoqiang;  Tan, Fei;  Li, Junde;  Chen, Junren;  Yu, Wei Han; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
5t-sram  Analog Non-uniform Quantization (Anuq)  Computing-in-memory (Clm)  Machine Learning (Ml)  Matrix-vector Multiplication (Mvm)  Partial Sum Boosting (Psb)  
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro Journal article
Fu, Yuzhao, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Zhang, Minglei, Martins, Rui P., Mak, Pui In. FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Fu, Yuzhao;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang;  Zhu, Yan; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.6/5.6 | Submit date：2024/05/16
Analog Partial Sum (Aps)  Compute-in-memory (Cim)  Convolutional Neural Network (Cnn)  Flexible Kernel Size  Utilization  
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor Journal article
Cheng, Kai, Chen, Yong, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Cheng, Kai;  Chen, Yong;  Stefano, Crovetti Paolo;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/06/05
Analog-to-digital Converter (Adc)  Capacitive Digital-to-analog Converters (Cdacs)  Cryptography  Entropy  National Institute Of StAndards And Technology (Nist)  Successive Approximation Register (Sar)  Thermal Noise  True Random Number Generator (Trng)  
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:  Tan, Gaofeng;  Qin, Xinyu;  Liu, Yan;  Guo, Mingqiang;  Sin, Sai Weng; et al.
Favorite | TC[WOS]:3 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2024/02/23
0-x Mash  Analog-to-digital Converter (Adc)  Anti-aliasing Filtering  Continuous Time (Ct)  Maximum Stable Amplitude (Msa)  Multi-stage Noise Shaping (Mash)  
A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator Journal article
Zhang, Hongshuai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Second-Order NS Pipelined SAR ADC with Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3565-3575.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:2 TC[Scopus]:4  IF:4.6/5.6 | Submit date：2024/01/02
Analog-to-digital Converter (Adc)  Auxiliary Noise Shaping (Ns) Successive-approximation Register (Sar) Adc  Capacitor Stacking  Data-weighted Averaging And detect-And-skip (Dwa And Das)  Differential Sampling  Energy Efficient  Error SupprEssion (Es) And Reconstruction  Gain Error Shaping (Ges)  Partial Time Interleaving  Passive Ns  Pipelined Sar  Quantization Predication Unrolled  Two-step Floating Inverter Amplifier (Fia)  
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching  
Analog and Mixed-Signal CMOS Circuits: The emergence and leadership of a Lab, a reference Book and the future at the core of the A/D Interface in the IoE Conference paper
Martins, Rui P.. Analog and Mixed-Signal CMOS Circuits: The emergence and leadership of a Lab, a reference Book and the future at the core of the A/D Interface in the IoE[C], 2023, 465-468.
Authors:  Martins, Rui P.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/02/22
Analog And Mixed-signal Vlsi (ams-Vlsi)  Integrated Circuits (Ics)  Internet Of Everything (Ioe)  State Key Lab (skLab)