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A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs Journal article
Lu, Zhifei, Zhang, Boyuan, Peng, Yutao, Peng, Xizhu, Tang, He, Pu, Jie, Qin, Ling, Guo, Mingqiang. A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025, 72(1), 48-52.
Authors:  Lu, Zhifei;  Zhang, Boyuan;  Peng, Yutao;  Peng, Xizhu;  Tang, He; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/12/26
Background Calibration  Fast Convergence  Neural-network-based Extraction Module  Nn-based Calibration  Time-interleaved Adc (Ti Adc)  Timing Mismatch Calibration  
A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation Journal article
Zhang, Ran, Cen, Xueru, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Martins, Rui P., Sin, Sai Weng. A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025, 1-13.
Authors:  ; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2025/01/22
Dac Driver  Dynamic Amplifier  Machine Learning (Ml)  Mixed-signal Multiply-and-accumulate (Mac)  Multi-bit Neural Network  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  ZHANG RAN;  UN KA FAI;  GUO MINGQIANG;  QI LIANG;  XU DENGKE; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/08/19
Machine Learning  Edge Computation  Computing-in-memory  Delta-sigma Converter  Floating Inverter Amplifier  
Research and Development on Key Integrated Circuit Technologies for Future Intelligent Robots Project
项目类型: Key R&D Projects, 项目编号: FDCT 0004/2023/AKP, 2024-2027
Authors:  Sai-Weng Sin;  Man-Kay Law;  Yan Lu;  Chi-Seng Lam;  Mingqiang Guo
Favorite |  | Submit date：2024/08/31
A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter Conference paper
Gong, Haoyu, Zeng, Wen Liang, Guo, Mingqiang, Lam, Chi Seng, Zhao, Shulin, Martins, Rui Paulo, Sin, Sai Weng. A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 18-4.
Authors:  Gong, Haoyu;  Zeng, Wen Liang;  Guo, Mingqiang;  Lam, Chi Seng;  Zhao, Shulin; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2024/06/05
Regulators  Power Supplies  Capacitors  Dc-dc Power Converters  Interference  System-on-chip  Noise Shaping  
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation Conference paper
Zhang, Ran, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Xu, Dengke, Zhao, Weibing, Martins, R. P., Maloberti, Franco, Sin, Sai Weng. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C], 2024.
Authors:  Zhang, Ran;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang;  Xu, Dengke; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/08/05
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering Conference paper
Li, Ke, Congzhou, Xianyu, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 28-5.
Authors:  Li, Ke;  Congzhou, Xianyu;  Qi, Liang;  Guo, Mingqiang;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/06/05
Wireless Communication  Computed Tomography  Pipelines  Capacitors  Low-pass Filters  Linearity  Lattices  
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering Journal article
Li, Ke, Gong, Haoyu, Xianyu, Congzhou, Li, Zhensheng, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Ke;  Gong, Haoyu;  Xianyu, Congzhou;  Li, Zhensheng;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2025/01/13
Analog-to-digital Converter (Adc)  Cascade Of Integrators With Feedforward (Ciff)  Continuous Time (Ct)  Ct Pipeline (Ctp)  Excess Loop Delay (Eld)  Low-pass Filter (Lpf)  Multistage Noise-shaping (Mash)  Offset Calibration  Signal Transfer Function (Stf) Peaking  
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:  Tan, Gaofeng;  Qin, Xinyu;  Liu, Yan;  Guo, Mingqiang;  Sin, Sai Weng; et al.
Favorite | TC[WOS]:3 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2024/02/23
0-x Mash  Analog-to-digital Converter (Adc)  Anti-aliasing Filtering  Continuous Time (Ct)  Maximum Stable Amplitude (Msa)  Multi-stage Noise Shaping (Mash)  
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching