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Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction Journal article
Xu, Tailong, Li, Haoran, Meng, Xi, Zhan, Xiangxun, Peng, Yatao, Yin, Jun, Yang, Shiheng, Fan, Chao, Huang, Zhixiang, Martins, Rui P., Mak, Pui In. Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.
Authors:  Xu, Tailong;  Li, Haoran;  Meng, Xi;  Zhan, Xiangxun;  Peng, Yatao; et al.
Favorite | TC[Scopus]:0  IF:4.0/3.7 | Submit date：2025/01/22
Gain-boosting Phase Detector  Jitter  Phase Noise  Phase-locked Loop  Reference Spur  Reference-sampling  
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS Journal article
Liu, Yueduo, Zhu, Zihao, Bao, Rongxin, Lin, Jiahui, Yin, Jun, Li, Qiang, Mak, Pui-In, Yang, Shiheng. A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 71(2), 515-525.
Authors:  Liu, Yueduo;  Zhu, Zihao;  Bao, Rongxin;  Lin, Jiahui;  Yin, Jun; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2024/03/13
Allan Deviation  Cmos  Energy Efficiency  Internet Of Things (Iot)  Rc Oscillator  Relaxation Oscillator  Small Area  Temperature Stability  Timing Accuracy  Ultra-low-power  
A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA Journal article
Yan Zeng, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Xiong Zhou, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li. A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA[J]. IEEE Sensors Journal, 2023, 23(18), 21747-21756.
Authors:  Yan Zeng;  Shiheng Yang;  Yueduo Liu;  Rongxin Bao;  Zihao Zhu; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:4.3/4.2 | Submit date：2023/10/10
Background Subtraction  Bad Pixel Compensation  Digital Readout Integrated Circuit (Droic)  Image Algorithm  Infrared Focal Plane Arrays (Irfpas)  Nonuniformity Correction  Pixel Analog-to-digital Converter (Adc)  
Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art Journal article
Shiheng Yang, Jun Yin, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Qiang Li, Pui-In Mak, Rui P. Martins. Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art[J]. Chip, 2023, 2(2), 1-10.
Authors:  Shiheng Yang;  Jun Yin;  Yueduo Liu;  Rongxin Bao;  Zihao Zhu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2023/08/19
Clock Generation, Ic Design, Phase-locked Loop (Pll), Frequency Synthesizer  
A 0.0043-mm 0.085- W/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network Journal article
Wei,Yuchen, Yang,Shiheng, Liu,Yueduo, Bao,Rongxin, Zhu,Zihao, Lin,Jiahui, Zhang,Zehao, Chen,Yong, Yin,Jun, Mak,Pui In, Li,Qiang. A 0.0043-mm 0.085- W/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31(8), 1248-1252.
Authors:  Wei,Yuchen;  Yang,Shiheng;  Liu,Yueduo;  Bao,Rongxin;  Zhu,Zihao; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:2.8/2.8 | Submit date：2023/08/03
Charge-prestored  Cmos  Energy Efficient  Inverter-based  Low Power  R-rc  Relaxation Oscillator  
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up Journal article
Zhang, Zehao, Yang, Shiheng, Liu, Yueduo, Zhu, Zihao, Lin, Jiahui, Bao, Rongxin, Xu, Tailong, Yang, Zhizhan, Zhang, Mingkang, Liu, Jiaxin, Zhou, Xiong, Yin, Jun, Mak, Pui In, Li, Qiang. On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 26-30.
Authors:  Zhang, Zehao;  Yang, Shiheng;  Liu, Yueduo;  Zhu, Zihao;  Lin, Jiahui; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3  IF:4.0/3.7 | Submit date：2023/01/30
Bluetooth Low-energy (Ble)  Crystal Oscillator (Xo)  Dc Settling  Duty Cycling  Energy Harvesting  Energy Injection  Initial Motional Current  Internet Of Things (Iot)  Low Power  Startup  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
Liu, Yueduo, Bao, Rongxin, Zhu, Zihao, Yang, Shiheng, Zhou, Xiong, Li, Qiang, Yin, Jun, Mak, Pui In. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(2), 495-505.
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2022/03/04
Voltage-controlled Oscillators  Jitter  Clocks  Phase Noise (Pn)  Topology  Performance Evaluation  Delays  Figure Of Merit (Fom)  Injection-locked Clock Multiplier (Ilcm)  Multiplying Delay-locked Loop (Mdll)  Power  Ring Voltage-controlled Oscillator (Rvco)  
A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/08/19
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108 - 3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/01/25
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power