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A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Journal article
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui In Mak, Franco Maloberti, Rui P. Martins. A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2022, 57(5), 1358-1371.
Authors:  Xiaoteng Zhao;  Yong Chen;  Lin Wang;  Pui In Mak;  Franco Maloberti; et al.
Favorite | TC[WOS]:10 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2022/05/13
And Zero Net Current (Znc)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Four-level Pulse-amplitude Modulation (Pam)  Frequency Detector (Fd)  Half-rate  Negative Net Current (Nnc)  Positive Net Current (Pnc)  Reference-less  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
Zhao, Xiaoteng, Chen, Yong, Mak, Pui In, Martins, Rui P.. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:13  IF:4.6/5.6 | Submit date：2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase Conference paper
Zhao, Xiaoteng, Chen, Yong, Zheng, Xuqiang, Mak, Pui In, Martins, Rui P.. A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase[C], 2021, 386-389.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Zheng, Xuqiang;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:4 | Submit date：2021/12/08
Bang-bang Clock And Data Recovery (Bbcdr)  Clock Selection  Cmos  Frequency Acquisition  Frequency Detector (Fd)  Reference (Ref)  Ring Oscillator (Ro)  Strobe Point (Sp)  
A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS Conference paper
Zhao, Xiaoteng, Chen, Yong, Wang, Lin, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS[C], 2021, 131-134.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco; et al.
Favorite | TC[WOS]:6 TC[Scopus]:9 | Submit date：2021/09/20
4-level Pulse Amplitude Modulation (Pam-4)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Frequency Detector (Fd)  Half-rate  Negative (Nnc) Net Current  Positive (Pnc)  Reference Less  Single Loop  Zero (Znc)  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[Scopus]:16 | Submit date：2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
Yang,Zunsong, Chen,Yong, Yang,Shiheng, Mak,Pui In, Martins,Rui P.. A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector[J]. IEEE Access, 2019, 8, 2222-2232.
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:20  IF:3.4/3.7 | Submit date：2021/03/09
Cmos  Dual Loop  Phase-locked Loop (Pll)  Frequency Detector (Fd)  Phase Detector (Pd)  Figure-of-merit (Fom)  Millimeter (Mm)-wave  Voltage-to-current Converter (Vic)  Voltage-controlled Oscillator (Vco)  Divider-by-4  Dynamic Latch