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Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment Journal article
Li, Haoran, Xu, Tailong, Meng, Xi, Yin, Jun, Martins, Rui P., Mak, Pui In. A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:  Li, Haoran;  Xu, Tailong;  Meng, Xi;  Yin, Jun;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/10/10
Fast Locking  Frequency Synthesis  Frequency-locked Loop (Fll)  Low Jitter  Millimeter-wave (Mm-wave)  Phase-locked Loop (Pll)  Reference (Ref.) Spur  Sub-sampling Phase Detector (Sspd)  Voltage-controlled Oscillator (Vco)  
A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM Journal article
Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Feng, Chaoping, Chen, Tianle, Zhang, Xinming, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Iizuka, Tetsuya, Chen, Yong, Mak, Pui In, Han, Zhengsheng, Li, Bo. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551.
Authors:  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Feng, Chaoping;  Chen, Tianle; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2  IF:0/0 | Submit date：2024/05/16
Double Sampling (Ds)  Figure Of Merit (Fom)  Frequency Synthesizer  Low Jitter  Low Spur  Phase Detector (Pd)  Phase-locked Loop (Pll)  Phase Noise (Pn)  Reference Sampling (Rs)  Subsampling (Ss)  Phase Locked Loops  Type-i  
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation Conference paper
Shen, Xinyu, Zhang, Zhao, Chen, Yong, Li, Yixi, Zhang, Yidan, Li, Guike, Qi, Nan, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMsJitter,-271.5dB FoMN, and Sub-10% Jitter Variation[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Shen, Xinyu;  Zhang, Zhao;  Chen, Yong;  Li, Yixi;  Zhang, Yidan; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/06/05
Temperature Sensors  Phase Noise  Linearity  Voltage  Detectors  Jitter  Delay Lines  
A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout Journal article
Peng, Yatao, Benserhir, Jad, Castaneda, Mario, Fognini, Andreas, Bruschini, Claudio, Charbon, Edoardo. A 0.32 × 0.12 mm2 Cryogenic BiCMOS 0.1–8.8 GHz Low Noise Amplifier Achieving 4 K Noise Temperature for SNWD Readout[J]. IEEE Transactions on Microwave Theory and Techniques, 2024, 72(4), 2179-2192.
Authors:  Peng, Yatao;  Benserhir, Jad;  Castaneda, Mario;  Fognini, Andreas;  Bruschini, Claudio; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.1/4.2 | Submit date：2024/05/02
Bicmos  Cryogenic Temperatures  Low-noise Amplifiers  Sige Heterojunction Bipolar Transistor (Hbt)  Superconducting Single-photon Detectors  Timing Jitter  
A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller Journal article
Chen, Wen, Shu, Yiyang, Yin, Jun, Mak, Pui In, Gao, Xiang, Luo, Xun. A 21.8-41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller[J]. IEEE Transactions on Microwave Theory and Techniques, 2024.
Authors:  Chen, Wen;  Shu, Yiyang;  Yin, Jun;  Mak, Pui In;  Gao, Xiang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.1/4.2 | Submit date：2024/05/16
Detectors  Fast Locking  Frequency Locked Loops  Jitter  Jitter  Millimeter Wave (mm-Wave)  Phase Locked Loops  Phase Noise  Subsampling Phase-locked Loop (Sspll)  Voltage-controlled Oscillators  Wideband  Wideband  
A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM Conference paper
Ren, Hongyu, Huang, Yunbo, Yang, Zunsong, Chen, Tianle, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Li, Zhongmao, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs JitterRMS, -91.9-dBc Reference Spur and -259-dB Jitter-Power FOM[C]:IEEE Computer Society, 2024, 113-116.
Authors:  Ren, Hongyu;  Huang, Yunbo;  Yang, Zunsong;  Chen, Tianle;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/12/05
Clock Generator  Frequency Synthesizer  Low Jitter  Low Power  Low Spur  Phase-locked Loop (Pll)  Reference Sampling  Type-ii  
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur Journal article
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui P. Martins. A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMS Jitter, −258.7-dB FOM, and −75.17-dBc Reference Spur[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 188-198.
Authors:  Yunbo Huang;  Yong Chen;  Bo Zhao;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:9  IF:2.8/2.8 | Submit date：2023/02/22
Cmos  Figure-of-merit (Fom)  Harmonic-rich Voltage-controlled Oscillator (Vco)  Integrated Jitter, Phase-detection Gain (Kpd)  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  Reference (Ref) Feedthrough Suppression  Type-i  Type-ii  
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference Journal article
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4799-4809.
Authors:  Yu Duan;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Digital-regulated Supply Noise Cancellation (Dsnc)  Interference Reduction  Jitter  Phase Noise Cancellation (Pnc)  Phase-locked Loop  Phase-locked Loop (Pll)  Ring Voltage-controlled Oscillator (Rvco)  Supply Noise Suppression