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A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation
Conference paper
ZHANG RAN, UN KA FAI, GUO MINGQIANG, QI LIANG, XU DENGKE, ZHAO WEIBING, RUI P. MARTINS, FRANCO MALOBERTI, SIN SAI WENG. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C]:IEEE, 2024.
Authors:
ZHANG RAN
;
UN KA FAI
;
GUO MINGQIANG
;
QI LIANG
;
XU DENGKE
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2024/08/19
Machine Learning
Edge Computation
Computing-in-memory
Delta-sigma Converter
Floating Inverter Amplifier
A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter
Conference paper
Gong, Haoyu, Zeng, Wen Liang, Guo, Mingqiang, Lam, Chi Seng, Zhao, Shulin, Martins, Rui Paulo, Sin, Sai Weng. A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 18-4.
Authors:
Gong, Haoyu
;
Zeng, Wen Liang
;
Guo, Mingqiang
;
Lam, Chi Seng
;
Zhao, Shulin
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2024/06/05
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS
Conference paper
Qin, Xinyu, Jin, Yichen, Wang, Guoxing, Sin, Sai Weng, Ortmanns, Maurits, Lian, Yong, Qi, Liang. A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 199537.
Authors:
Qin, Xinyu
;
Jin, Yichen
;
Wang, Guoxing
;
Sin, Sai Weng
;
Ortmanns, Maurits
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
1
|
Submit date:2024/06/05
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation
Conference paper
Zhang, Ran, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Xu, Dengke, Zhao, Weibing, Martins, R. P., Maloberti, Franco, Sin, Sai Weng. A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation[C], 2024.
Authors:
Zhang, Ran
;
Un, Ka Fai
;
Guo, Mingqiang
;
Qi, Liang
;
Xu, Dengke
; et al.
Favorite
|
TC[Scopus]:
0
|
Submit date:2024/08/05
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering
Conference paper
Li, Ke, Congzhou, Xianyu, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:
Li, Ke
;
Congzhou, Xianyu
;
Qi, Liang
;
Guo, Mingqiang
;
Martins, Rui P.
; et al.
Favorite
|
TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2024/06/05
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing
Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:
Guo Mingqiang
;
Qi Liang
;
Zhao Weibing
;
Xiao Gangjun
;
Rui P. Martins
; et al.
Adobe PDF
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Favorite
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TC[WOS]:
1
TC[Scopus]:
1
IF:
5.2
/
4.5
|
Submit date:2023/08/21
Analog-to-digital Converter (Adc)
Successive Approximation Register (Sar)
Power-delay-optimized
Unbalanced N/p-mos Sizing Buffers
Monotonic Switching
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA
Journal article
Tan, Gaofeng, Qin, Xinyu, Liu, Yan, Guo, Mingqiang, Sin, Sai Weng, Wang, Guoxing, Lian, Yong, Qi, Liang. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792.
Authors:
Tan, Gaofeng
;
Qin, Xinyu
;
Liu, Yan
;
Guo, Mingqiang
;
Sin, Sai Weng
; et al.
Favorite
|
TC[WOS]:
3
TC[Scopus]:
4
IF:
5.2
/
4.5
|
Submit date:2024/02/23
0-x Mash
Analog-to-digital Converter (Adc)
Anti-aliasing Filtering
Continuous Time (Ct)
Maximum Stable Amplitude (Msa)
Multi-stage Noise Shaping (Mash)
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications
Journal article
Pan,Caolei, Zeng,Wen Liang, Lam,Chi Seng, Sin,Sai Weng, Zhan,Chenchang, Martins,Rui P.. A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3219-3230.
Authors:
Pan,Caolei
;
Zeng,Wen Liang
;
Lam,Chi Seng
;
Sin,Sai Weng
;
Zhan,Chenchang
; et al.
Favorite
|
TC[WOS]:
3
TC[Scopus]:
3
IF:
4.6
/
5.6
|
Submit date:2023/08/03
Adaptive Sizing
Clocked-feedback Resistor Network (Cfrn)
Discontinuous Conduction Mode (Dcm)
Double Clock Timing (Dct) Control
Modified Ky (m-Ky) Converter
Wide Load Range
A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator
Journal article
Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi. A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 1-13.
Authors:
Yue Hu
;
Yuekai Liu
;
Xinyu Qin
;
Yan Liu
;
Mingqiang Guo
; et al.
Adobe PDF
|
Favorite
|
TC[WOS]:
2
TC[Scopus]:
2
IF:
5.2
/
4.5
|
Submit date:2023/08/22
Continuous-time Delta-sigma Modulator (Dsm)
Time-interleaved (Ti)
Cascaded Integrator Of Distributed Feedforward (Ciff)
Excess Loop Delay (Eld) Compensation
A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA
Journal article
Tan Gaofeng, Qin Xinyu, Liu Yan, Guo Mingqiang, Sin Sai-Weng, Wang Guoxing, Lian Yong, Qi Liang. A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023.
Authors:
Tan Gaofeng
;
Qin Xinyu
;
Liu Yan
;
Guo Mingqiang
;
Sin Sai-Weng
; et al.
Adobe PDF
|
Favorite
|
IF:
5.2
/
4.5
|
Submit date:2023/08/22
Multi-stage Noise Shaping , Topology , Delays , Robustness , Quantization (Signal) , Calibration , Thermal Stability